Modern large scale integrated circuits (ICs) are often required to implement various different functionalities. For an IC to implement each of its different functionalities optimally, it must have available different clock sources supplying different types of clocks. Sometimes the different functionalities in the IC require clocks that are of different frequencies. Sometimes the different functionalities require clocks that are of the same frequency but at different phases.
Circuit elements in the IC that operate using a same clock signal are sometimes said to be in a same clock domain. In order for circuit elements in a clock domain to function as intended, the clock signal must arrive at all storage and sequential circuit elements (e.g., flip-flops and memories) in that clock domain at precisely determined time. To accomplish this, each clock domain includes a clock distribution network, which is physically designed to ensure that each storage or sequential element in the clock domain receives the clock signal at about the same time.
In addition to the distribution network for the clock signal, a clock domain sometimes has to include distribution networks for high-fan out control signals as well. A control signal turns on or off a particular functionality in an IC, often by enabling, disabling or resetting a group of storage or sequential elements. In order for the particular functionality to behave predictably, it is important that every sequential or storage element in the group receives the control signal at the same clock cycle. This requires the control signal that controls the group of sequential or storage elements be synchronized to the clock of the clock domain. This also requires the clock domain to include a distribution network for the control signal when the number of sequential elements is large.
As ICs become larger and the functionalities implemented on the ICs become more complex, the number of clock domains has increased while the fan-outs of the control signals in the clock domains have grown. Control signals such as enable and reset have thus become high fan-out signals requiring high fan-out distribution schemes such as balance trees and pipeline stages. In many of these instances, a clock domain is defined by its control signal distribution networks in addition to its clock distribution network. These distribution networks generally have stringent timing requirements and must be physically designed into the IC prior to fabrication.
In non-configurable ICs such as Microprocessors and ASICs, interconnecting multiple circuit elements with multiple clock sources is generally manageable, because each circuit element in each clock domain has a pre-determined and non-configurable relationship with a clock source. However, in an IC that has a large number of configurable circuits (e.g., an FPGA or a PLD), the configurability of the IC requires that each of the many circuit elements be configurably paired with one of the many possible clock sources. The complexity of the required interconnections in such an IC is thus significantly greater than that of Microprocessors and ASICs. As the size of modern configurable IC has grown considerably larger, the interconnections needed to implement some or all of the possible permutations of clock/configurable circuit pairings has become nearly unmanageable.
Therefore, there is a need for efficient management of interconnections between multiple clock sources and a large number of configurable circuits.